Hrushikesh Vasuki (Rishi)
48, Chapin Complex
Stony Brook
NY 11790 		Email: hvasuki@ece.sunysb.edu
Phone: (631) 216 2235 (Res)
(631) 948 1976 (Cell)
web/url: http://www.sinc.sunysb.edu/Stu/hvasuki/
OBJECTIVE To obtain a full-time engineering related position where I can utilize my skills in Design & Development in core areas of Embedded Systems / Communication & Digital Signal Processing
EDUCATION
  • M.S. in Electrical Engineering at SUNY, Stony Brook, majoring in Communication & Signal Processing, expected May 2001
  • Bachelor of Engineering (B.E.) at S.J. College of Engineering, Mysore, India, majoring in Electronics & Communication, graduated in August 1998
    GPA Equivalent 3.67
    • RELATED COURSES
  • Traffic Performance: Wireless & Mobile Communication Systems
  • Digital Communications
  • Linear Systems
  • Digital Signal Processing
  • Statistical Signal Processing
  • Information Theory & Coding
  • Optimization Techniques
  • Computer Architecture
  • Computer Networks

    • SKILLS
    Simulators: MATLAB 5.0
    Languages: C, C++, VHDL
    Assembly/DSP: 8085, 8086, ADSP 21xx , TMS 320c2x , TMS c6201 Fixed Point & TMS c6701 Floating Point Processors
    Operating Systems: Windows NT/98/95, Unix
    Web Development: HTML, VB Script for ASP, Javascript

    RELATED WORK EXPERIENCE
    Sept 1998-Aug 1999: Embedded Systems Design Engineer
    Icube Labs, Bangalore, India
  • Involved in the design & implementation of an MPEG-I, Layer-III (MP3) Audio Decoder on the Analog Devices ADSP-2185 Fixed Point Processor
  • Wrote the detailed design document
  • Reviewed the open source C-code
  • Directly involved with the implementation of the Huffman Decoding and the Joint Stereo Processing modules.
  • An older version of related documentation is available here
  • The entire decoder was coded in ADSP 2185 assembly

    • RELATED PROJECTS
    Spring 2001 : Term Project for ESE 545 - Computer Architecture
  • The implications of branch prediction on the performance of a Tomasulo’s dynamic scheduling algorithm based DLX processor with a single data bus
  • The entire simulation is being carried out in C language
  • The project involves the design and simulation of a DLX processor with multiple functional units (integer and floating point adders, multipliers, load and store buffers etc.) with capabilities of branch prediction and bus contention resolution for the single data bus
    • Spring 2001 : Teaching Assistant for ESE 344-Software Tools in Engineering : A course that teaches engineering students C, C++, Java & Shell scripting in the Unix environment
    Fall 1999 : Term Paper for ESE 505 Wireless & Mobile Communications, Stony Brook
    "Orthogonal Frequency Division Multiplexing (OFDM) : A comparison between OFDM, CDMA & TDMA"
    Spring 1998 : Senior Design Project at Mysore University, India
    Design and simulation of a Speech Coder on MATLAB using Sinusoidal Coding algorithms for Voiced & Unvoiced speech segments.
    Fall 1997 : Project entry for TI- DSP Worldwide Challenge
    Design & implementation of Adaptive Differential Pulse Code Modulation (ADPCM) on a TMS 320c2x Fixed Point Processor.

    WORK EXPERIENCE
    Fall 1999-Present Webmaster / Graduate Assistant
    Career Center at SUNY, Stony Brook,NY
    Created & maintained the Career Center’s website (www.career.sunysb.edu). Designed and implemented a variety of Online forms, Search Engines, Data-driven pages, Dynamic text version etc. using ASP (Active Server Pages) and Javascript.

    REFERENCES
    Available upon request